The present invention relates to a semiconductor device and a method of fabricating the same. More specifically, the invention relates to a semiconductor device including a plurality of transistors, and a plurality of load or capacitance elements, and a method of fabricating the same.
A static random-access memory (hereinafter abbreviated to xe2x80x9cSRAMxe2x80x9d) will be described as an example of conventional semiconductor devices. A conventional flip-flop SRAM cell comprises two load elements and four n-channel MOS transistors, as described in JP-B No. 7-112014, and T. Yamanaka, T. Hashimoto et al. xe2x80x9cA 25 xcexcm2, New poly-Si PMOS Load (PPL) SRAM Cell Having Excellent Soft Error Immunityxe2x80x9d, IEDM ""88.
FIG. 75 illustrates an equivalent circuit of a conventional flip-flop SRAM cell, wherein the drain D of each of a pair of drive MOS transistors T1 and T2 is connected to the gate electrode G of the other. Load elements, for example, load resistors R1 and R2 of high-resistance polysilicon, are connected to the drains D of the drive MOS transistors T1 and T2. The sources S of the drive MOS transistors T1 and T2 are maintained at a predetermined potential, for example a ground potential, and a supply voltage VCC is applied to the other ends of the load resistors R1 and R2. Supply voltage Vcc supplies a small current to a flip-flop circuit including the drive MOS transistors T1 and T2, and the load resistors R1 and R2. Access MOS transistors T3 and T4 are connected to storage nodes N1 and N2. The four MOS transistors T1 to T4, and the two load resistors R1 and R2 constitute a cell of one bit. In FIG. 75, reference numeral 10a represents a word line and reference numerals 50a and 50b represent bit lines.
FIG. 76 is an equivalent circuit of a flip-flop SRAM cell provided with thin-film transistors (xe2x80x9cTFTsxe2x80x9d) as load elements. Generally, load elements are high-resistance polysilicon resistors or thin-film transistors.
The prior art will be described in detail with reference to FIGS. 77 to 86. FIGS. 77 to 81 illustrate the structure of a conventional SRAM cell of a highresistance load type for one bit and a method of fabricating the same. FIGS. 77 to 80 show a planar layout of each layer forming a SRAM cell for one bit. FIG. 81 is a sectional view taken on line Y1-Y2 of FIGS. 77 to 80.
FIG. 77 is a planar layout of access MOS transistors and drive MOS transistors, including a first conductive film serving as a gate electrode. FIG. 78 is a pattern of a second conductive film of high-resistance polysilicon formed in part of a polysilicon film. FIG. 79 is a pattern of a third conductive film. FIG. 80 is a pattern of a fourth conductive film forming aluminum lines.
Referring to FIG. 77, a word line 10a formed by patterning a first conductive film serves as a common gate shared by access MOS transistors T3 and T4. The drains 6a and 6b, i.e., diffused layers, of the access MOS transistors T3 and T4 are connected through viaholes 21a and 21b to members 30a and 30b of a third conductive film, as shown in FIGS. 79 and 81. The drains 6a and 6b are also connected through viaholes 42a and 42b to bit lines 50a and 50b, i.e., portions of a fourth conductive film of aluminum or the like as shown in FIGS. 80 and 81.
The gate electrodes 10b and 10c of drive MOS transistors T2 and T1 are connected through viaholes 5a and 5c to the sources 6c and 6d of the access MOS transistors T3 and T4, respectively. The sources of the drive MOS transistors T1 and T2 are connected through viaholes 21c and 21d by a third conductive film 30c as shown in FIG. 79. A ground potential VSS is applied through the third conductive film 30c to the sources of all the drive MOS transistors of the SRAM.
The sources 6c and 6d, i.e., diffused layers, of the access MOS transistors T3 and T4 are connected through viaholes 12a and 12b to low-resistance polysilicon films 20a and 20b, and to resistors, i.e., high-resistance films, 20R1 and 20R2, respectively, as shown in FIG. 78. As shown in FIG. 78, a second conductive film 20c forms a power feed line for applying a supply voltage VCC to high-resistance elements R1 and R2.
FIGS. 82 to 86 illustrate the structure of the one cell for one bit of the conventional SRAM of a TFT load type shown in FIG. 76. FIGS. 82 to 85 show the planar layout of each cell in different phases of the fabricating process. FIG. 86 is a sectional view taken on line Y1-Y2 in FIGS. 82 to 85.
FIG. 82 is a planar layout of access MOS transistors and drive MOS transistors including a first conductive film forming gate electrodes. FIG. 83 is a plan view of a second conductive film serving as a lower gate electrode of a TFT. FIG. 84 is a plan view of a third conductive film serving as a channel of the TFT. FIG. 85 is a plan view of aluminum wiring lines formed by patterning a fifth conductive film.
Referring to FIG. 82, a word line 10a is a common gate shared by access MOS transistors T3 and T4. The drain 6b, i.e., a diffused layer, of the access MOS transistor T4 is connected through a viahole 32b to a fourth conductive film 40b. The drain 6b is also connected through a viahole 41b to bit lines 50a and 50b, i.e., aluminum wiring lines formed by patterning a fifth conductive film as shown in FIGS. 85 and 86. Similarly, the drain 6a, i.e., a diffused layer, of the access MOS transistor T3 is connected through a viahole 32a to a fourth conductive film 40a. The drain 6a is also connected through a viahole 41a to the bit lines 50a and 50b, i.e., aluminum wiring lines formed by patterning the fifth conductive film.
The sources 6c and 6d of the access MOS transistors T3 and T4 are connected through viaholes 5a and 5c to the gate electrodes 10b and 10c of drive MOS transistors T2 and T1, respectively, as shown in FIG. 82. The sources of the drive MOS transistors T1 and T2 are interconnected by a diffused region, as shown in FIG. 82. A first conductive film 10d is connected to the sources of all the drive MOS transistors of the SRAM to apply a ground potential VSS to the sources.
TFTs T5 and T6, i.e., load elements, comprise lower gate electrodes 20a and 20b formed by patterning a second conductive film of polysilicon (as shown in FIGS. 83 and 86), a second insulating film 21 serving as a gate oxide film (as shown in FIG. 86), and polysilicon channels 30a and 30b formed by patterning a third conductive film (as shown in FIGS. 84 and 86).
As shown in FIGS. 82 to 86, nodes N1 and N2, i.e., the diffused sources of the access MOS transistors T3 and T4, are connected through viaholes 12a and 21a and viaholes 12b and 21b to channel layers 30a and 30b formed by patterning a third conductive film, respectively. The opposite ends of the channel layers 30a and 30b are low-resistance polysilicon. The other end of the low-resistance polysilicon layer serves as a power feed line for feeding power of a supply voltage VCC.
The foregoing conventional SRAM cell has the following problems.
When forming the high-resistance polysilicon layer to be used as load elements and the TFTs in a layered structure on a memory cell, the high-resistance polysilicon layer and the TFTs are connected through the viaholes 5a and 5b to the gate electrodes 10b and 10c of the drive MOS transistors T1 and T2. Misalignment of masks (masks for forming the gate electrodes 10b and 10c of the drive MOS transistors T1 and T2 and the viaholes 12a and 12b, and masks for forming the viaholes 12a and 12b and the load elements) for forming the viaholes 5a and 5b and the gate electrodes 10b and 10c of the drive MOS transistors T1 and T2, results in an increase in the dimensions of those components (hereinafter referred to as xe2x80x9cCD gainsxe2x80x9d) and/or decrease in the dimensions of those components (hereinafter referred to as xe2x80x9cCD lossesxe2x80x9d). Therefore, when laying out the cells, sufficiently large superposing allowances must be secured. Such large superposing allowances increases the total member of the memory chip.
Trace uranium (U) and trace thorium (Th) contained in a ceramic material or a resin for packaging a memory chip, and in the material forming the wiring lines, emit alpha rays when they decay. If alpha rays penetrate the memory chip, electron-hole pairs are produced along the paths of alpha particles, and the potentials of the storage nodes N1 and N2 are varied by the electron-hole pairs. Consequently, a xe2x80x9csoft errorxe2x80x9d occurs, resulting in the loss of information stored in the memory cells.
Recently, soft error problems attributable to cosmic alpha rays have been reported. Neutrons are produced when cosmic alpha rays collide with the atmosphere. If the neutrons produced collide with Si nuclei in the memory chip, charged particles (including protons, alpha particles and heavy ions) are produced and the Si nuclei move. Consequently, a large quantity of charges are produced and cause the potentials of the storage nodes N1 and N2 to destroy information stored in the memory cells. In the conventional SRAM cell, charges necessary for compensating a charge loss caused by alpha rays and neutrons can be stored by using the pn junction capacitance. The capacitance is produced between the n+diffused layer forming the drains of the drive MOS transistors T1 and T2 and the p-type silicon substrate, and using the capacitance of insulating films, such as the gate oxide film and the layer insulating film. However, if the member for the memory cell is reduced in size, charges sufficient for compensating the charge loss caused by alpha rays and neutrons cannot be stored. Therefore, the soft error rate increases and the reliability is deteriorated greatly if the SRAM cell of the conventional structure is miniaturized.
When forming the load elements of high-resistance polysilicon and TFTs in a stacked structure on the memory cell, the layers for forming the load elements and the components of the TFTs are processed by photolithographic processes and etching processes. Therefore, the SRAM cell needs an increased number of processes and hence the yield of the SRAM cell is reduced.
Accordingly, it is an object of the present invention to provide a semiconductor device capable of being formed in a small member, highly resistant to soft errors and requiring a smaller number of fabricating processes than the conventional semiconductor device, and to provide a method of fabricating such a semiconductor device.
According to one aspect of the present invention, a semiconductor device comprises a semiconductor substrate. An underlying insulating film is formed over a major surface of said semiconductor substrate. A plurality of conductive films are formed on said underlying insulating film. Insulating films are formed between said plurality of conductive films. Further, at least two adjacent conductive films among said plurality of conductive films are interconnected through a viahole formed in said insulating film, and have the same planar shape.
In another aspect of the present invention, in the semiconductor device, said conductive film formed directly on said underlying insulating film among said plurality of conductive films is connected to said semiconductor substrate through a viahole formed in said underlying insulating film.
In another aspect of the present invention, in the semiconductor device, at least one of said plurality of conductive films has a high-resistance region.
In another aspect of the present invention, in the semiconductor device, a first additional conductive film is formed on at least one of said plurality of conductive films with an insulating film formed therebetween, and a thin-film transistor is formed by said conductive film among said plurality of conductive films and said first additional conductive film.
In another aspect of the present invention, in the semiconductor device, a gate electrode of said thin-film transistor is formed from said conductive film among said plurality of conductive films, and a channel of said thin-film transistor is formed from said first additional conductive film.
In another aspect of the present invention, in the semiconductor device, a channel of said thin-film transistor is formed from said conductive film among said plurality of conductive films, and a gate electrode of said thin-film transistor is formed from said first additional conductive film.
In another aspect of the present invention, in the semiconductor device, said first additional conductive film is formed with an insulating film sandwiched between said first additional conductive film and said conductive film among said plurality of conductive films, and a second additional conductive film is connected to said conductive film among said plurality of conductive films.
In another aspect of the present invention, in the semiconductor device, a channel of said thin-film transistor is formed from said first additional conductive film, and double gate electrodes are formed from said conductive film among said plurality of conductive films and said second additional conductive film connected to said former.
In another aspect of the present invention, in the semiconductor device, said first additional conductive film and said second additional conductive film are the same in planar shape.
According to another aspect of the present invention, a semiconductor device comprises a semiconductor substrate. An underlying insulating film is formed over a major surface of said semiconductor substrate. A surface conductive film is formed on said underlying insulating film. A plurality of conductive films are formed on said insulating base film. Insulating films are formed between said plurality of conductive films. Further, at least two adjacent conductive films among said plurality of conductive films are the same in planar shape, and one of said two adjacent conductive films is connected through a viahole formed in said insulating film to said surface conductive film.
In another aspect of the present invention, in the semiconductor device, said surface conductive film is connected through a viahole formed in said underlying insulating film.
In another aspect of the present invention, in the semiconductor device, at least one of said plurality of conductive films has a high-resistance region.
In another aspect of the present invention, in the semiconductor device, a gate electrode of a thin-film transistor is formed from one of said two conductive films, and a channel of said thin-film transistor is formed from said other conductive film.
In another aspect of the present invention, the semiconductor device further comprises a first additional conductive film formed so that one of said two conductive films is sandwiched between said first additional conductive film and said other conductive film with an insulating film sandwiched between said first additional conductive film and said one of said two conductive films.
In another aspect of the present invention, in the semiconductor device, a channel of a thin-film transistor is formed from one of said two conductive films, and double gate electrodes of said thin-film transistor are formed from said other conductive film and said first additional conductive film connected to said other conductive film.
According to another aspect of the present invention, in a method of fabricating a semiconductor device, a first conductive film is formed on an underlying insulating film formed on a semiconductor substrate. A first insulating film is formed on said first conductive film. An opening is formed through at least said first insulating film and said first conductive film. A second conductive film is formed on said first insulating film and in said opening. Further, said second conductive film, said first insulating film and said first conductive film are patterned in the same planar shape so as to include said opening.
Other features and advantages of the present invention will become more apparent from the following description taken together with the accompanying drawings.